How large is the gap between advertised compute power and actual output? At WAIC 2026, multiple industry insiders provided a concerning figure: less than 30%. This means that after an AI server is delivered to users, the effectively utilized compute power may not even reach one-third of the figure listed on its specification sheet.

This is not an isolated judgment. Chip companies across different domains have collectively shifted their narrative from "how much compute power" to "how well the compute power is utilized." This shift in framing itself is a signal: the AI industry has already crossed the first threshold of “feasibility” and is now advancing into the “usability” phase.

The core contradiction in this stage is migrating upward—from chip design to system-level integration.

Reasoning Surpasses Training: Not Prediction, but Reality

In 2024, industry capital flowed almost entirely toward training; by 2026, reasoning has surpassed training in compute demand volume.

Training chips aim for "better learning," while reasoning chips prioritize "greater efficiency." Fu Qingping, Senior Director of Commercial Products and Solutions at Xiwang Intelligence, stated that these two distinct design philosophies correspond to fundamentally different business models. The granularity of reasoning scheduling is evolving from task-level down to operator-level: "The finer the granularity, the higher the efficiency—each incremental gain in efficiency reduces token cost by a fraction." This implies that competition in reasoning chips has penetrated deep into model-layer scheduling efficiency—a dimension once considered purely software-related, now becoming a core selling point for chip products.

From the perspective of video processing, the surge in reasoning demand is even more evident. VPU vendors project that 80% of future videos will be AI-generated, and estimates suggest that video generation consumes 1,000 times more tokens than text generation. According to reports, offloading video-related computations from GPUs to dedicated chips via VPU+GPU co-processing could reduce video generation costs by up to 80%.

Yang Dawa, VP of Strategic Ecosystem at Houmo Intelligent, remarked: "Training determines the upper limit of model capability, while reasoning determines whether AI can achieve widespread deployment." As reasoning becomes the industrial axis, the demand structure within the chip industry is shifting. Cloud environments require scalable reasoning chips; video scenarios need VPUs; edge-side fast thinking demands NPUs; low-power edge reasoning calls for memory-compute integrated architectures. General-purpose GPUs are no longer the only answer—specialization has transitioned from theoretical discussion to commercial reality.

Compute Economics: Becomes Industry Consensus

Zhu Zhaoyuan, Co-founder and CEO of Rongming Microelectronics, believes the fundamental reason for reduced compute cost lies in efficiency gains. To understand hardware evolution, consider transportation upgrades: from horse carriages to cars to trains—same journey from point A to B, lower cost—but the real driver isn't "saving," but "efficiency improvement."

This explains why at WAIC 2026, many companies no longer lead with TOPS figures but instead emphasize "total cost of ownership (TCO)." Data center clients evaluate chip solutions across at least six dimensions: stability, performance, latency, power consumption, image quality, and TCO. The underlying truth behind the statement "customers don’t care what kind of PU you call it" is clear: when AI moves from lab to production, evaluation criteria aren’t exam scores—they’re real-world outcomes.

Reasoning chips reduce costs by hardware pruning of redundant training functions. This reflects the trend from general-purpose to specialized computing. From early CPUs to GPUs, then DPUs and VPUs, each specialization corresponds to a specific computational workload being extracted from general platforms. The VPU+GPU collaboration case, which successfully reduces costs, has already validated this trend commercially. Currently, the market choice for domestic chips to follow the GPU path is pragmatic. Hardware manufacturers must respond to market realities; products must evolve continuously without disruption. The lowest-risk strategy remains general-purpose GPUs. But beyond this, diverse compute chips will increasingly specialize into niche domains, giving rise to unicorns in specific segments.

Edge chip cost reduction relies on algorithm partners adapting to different use cases. If the product category is large enough—such as smartphones or automobiles—it can absorb customization costs. For other scenarios, coverage through a general-purpose foundation enables broader dissemination of cost-reduction benefits. From the edge perspective, challenges are more complex. The three core requirements for edge reasoning are privacy, cost, and low-latency interaction with the physical world—dimensions that define edge chip design logic, diverging sharply from cloud-centric approaches. Liu Jianwei, Co-founder and Vice President of Aixi Yuanzhi, highlighted the logical difference between cloud and edge: cloud-first prioritizes user experience before cost reduction, while edge-first focuses on cost before enhancing experience. This sequencing difference directly impacts chip design trade-offs. Consequently, the business model for edge AI is also evolving—when users realize subscription fees may exceed hardware cost, demand for one-time purchase models is emerging.

The AI chip industry is entering a mature phase where TCO is the central consideration. In this stage, software optimization and systems engineering capabilities may surpass raw hardware specifications in value.

A related divergence concerns where the next AI revolution will erupt. Some believe revolutions will occur simultaneously in the cloud (AI video generation) and at the edge (embodied intelligence); others define 2026 as the "Year of Physical AI," with robotics receiving the highest optimism; still others argue that the entire industry will see explosive growth, with the fastest adoption occurring in sectors most proficient in AI.

Year of Physical AI: Where Is Embodied Intelligence Now?

Embodied intelligence was frequently cited by multiple enterprises as the next breakthrough point. The robot exhibition area at WAIC provided evidence: unlike previous years’ performance-oriented robots—pouring water, boxing—this year’s robots can perform sustained, intricate tasks continuously, transitioning from exhibition booths into factory production lines.

However, the industrial form of embodied intelligence remains far from consolidated. One view holds a broad definition: any autonomous machine capable of performing work—like vacuum cleaners or lawn mowers—can be called a "robot." Another favors humanoid designs, arguing that all human infrastructure is designed for human form, making humanoid robots the most universally applicable hardware platform, with scalability driving down costs. Yet current humanoid manufacturing costs remain high, so the decisive factor will be which form achieves cost feasibility first.

Robots differ fundamentally from other terminals in their dependence on AI. A company pursuing memory-compute integration offered a sharp contrast: a PC without AI remains a PC, a car without AI remains a car—but a robot without AI is just scrap metal. This underscores the absolute necessity of edge-side AI for robots, reflected in three dimensions: privacy (data cannot go to the cloud), token cost (frequent cloud calls are prohibitively expensive), and real-time, safe physical interaction (no control failure in signal-deprived tunnels, commands cannot rely on cloud). In these areas, low power consumption and high energy efficiency of edge chips become critical variables, with memory-compute integrated architecture capable of improving power efficiency by one to two orders of magnitude.

For the embodied intelligence sector, data bottlenecks have already eased. Industry giants have amassed vast amounts of video and operational data; algorithms are largely viable—demonstrations at WAIC by multiple robotics firms confirm this. The real challenge lies in how efficiently algorithms run on available compute: model pruning, low power, and low latency must be jointly optimized—essentially a systems engineering problem.

Hundreds of embodied intelligence startups are testing applications across logistics, assembly, and companionship—but no consensus killer app has emerged yet. The underlying chip industry believes that opening a door to universal intelligence will naturally spawn countless applications.

Software Ecosystem: A Barrier Thicker Than Chips

If cost-efficiency is the destination of competition, the software ecosystem is the essential bottleneck on the path there. Returning to the massive gap between advertised compute power and actual output mentioned at the beginning, the root cause lies in model selection, fine-tuning, knowledge base construction, mid-to-low-level software stack optimization, and data center configuration. Delivering an AI server and implementing an AI project is like buying a wok and cooking a dish—the intermediate work is substantial.

The core barrier of a chip’s ecosystem isn’t just technical—it’s about developer habits. New architectures like memory-compute integration face a key challenge: it’s not that chips can’t be built, but that software ecosystems lag behind. Even if chip specs are impressive, significant effort remains in systems engineering: adaptation, tuning, and customer scenario refinement.

In edge-side AI scenarios, model iteration speeds are extremely rapid. Cloud-based large models have accelerated from six-month cycles to two-month cycles; edge models are similarly evolving quickly. Each model iteration requires re-adaptation to the chip, and the speed of engineering implementation directly determines commercialization velocity. "Turning a technology from usable to truly effective requires a lot of dirty, tedious work."

One perspective notes that mid-to-low-level software stacks can increase effective compute output by 2 to 5 times on identical hardware—but few discussions at this year’s WAIC focused deeply on this direction. Full-stack deployment demands collaboration among specialists across multiple domains: agents, model optimization, knowledge bases, underlying compute scheduling, and operations. Only when all these roles are aligned can a truly efficient full-stack solution emerge.

When asked whether domestic AI chips should prioritize performance or ecosystem development, one reasoning chip company responded: neither currently represents a bottleneck—what’s most lacking is industrial coordination.

From memory-compute integration to edge NPUs, from VPUs to full-stack integration, companies across different technical paths are unanimously pointing toward software ecosystems rather than hardware performance. There is industry consensus on the direction of specialized chip architectures—but substantial disagreements remain over the pace, depth, and ultimate form of specialization. The underlying logic of this divergence: is the fragmentation of AI application scenarios sufficient to sustain multiple specialized architectures coexisting, or will they eventually converge into a few dominant general-purpose platforms?

As hardware parameter competition nears diminishing returns, the battleground inevitably shifts upward to the software layer. This upward migration is precisely the critical window for domestic chips to transition from "chasing performance" to "chasing system maturity." Industry experts further note that the adoption rate of domestic ecosystems is already very high—colleges now teach directly on domestic platforms, and key customers prefer domestic ecosystems. This top-down ecosystem building is China’s unique advantage.

A more advanced assessment is that domestic AI chips currently face no bottleneck in either performance or ecosystem. Such a judgment would have been unthinkable three years ago. Chip parameters are already excellent, but systems engineering still requires immense work. The gap is no longer “can we,” but “how well.” A model scoring 70 or 80 points is already functional—but doing the job well isn’t about a single model or chip alone; it requires comprehensive support from toolchains, compilers, scheduling systems, and industry-specific adaptations. From AI inference chips to real-world deployment, extensive industrial collaboration is needed: solution partnerships, user scenario alignment, super-node network coordination—each link requires someone to act.

True full-stack integration samples do exist—spanning from CPU to software integration firms to hardware manufacturing—where conglomerate systems hold advantages in large-scale full-stack projects within key domains. However, such capabilities are not widespread; most companies remain operating in silos.

From the customer side, industry feedback indicates that data center chips typically require 6 to 24 months from initial contact to mass deployment—long test cycles and high onboarding barriers. This means even if chip technology meets standards, commercialization still requires a prolonged validation period. This cycle cannot be compressed by single-point technology alone; it demands deep collaboration among chip vendors, software suppliers, and end customers.

The AI chip industry in 2026 is undergoing a subtle transformation: the primary battlefield is shifting from wafer fabs and tape-out workshops to compilers, toolchains, and system scheduling layers. When multiple companies, starting from different technical routes, converge on the same chasm, it is no longer an individual opinion—it is a collective industry recognition.

Source: ICViews (ID: ICViews), Author: Liuqian

Source: ICViews