“How many GPUs are inside?” “Why such a large rack?” At the main exhibition area of the 2026 World Artificial Intelligence Conference (WAIC) held at Shanghai World Expo Exhibition Hall, several rows of two- to three-meter-tall, all-black racks consistently drew crowds.

Some people leaned in to examine liquid-cooling pipelines; others raised their phones to photograph high-speed cabling coiled atop the racks; still others chased after staff members asking what kind of work this rack’s compute power could actually perform.

Huawei Atlas 950 SuperPoD, ZTE OEX, Alibaba Cloud Zhenwu M890 × Panjue AL128… It's rare for infrastructure to become a star exhibit at a trade show—but SuperPoDs have achieved exactly that.

Over four days, reporters from IT Times wandered through the exhibition floor, interviewing multiple chip and equipment manufacturers investing heavily in SuperPoDs, seeking to understand one key question: Why has this concept—once merely a buzzword among a few enterprises—suddenly become everyone’s shared choice?

The Same Direction, Different Paths

If last year’s WAIC saw SuperPoDs as a niche new concept showcased by only a handful of companies, this year they’ve become a collective consensus across China’s domestic computing industry.

From Huawei, Biren, Sichuan, ZTE Communications, Muxi Inc., to Inspur, Alibaba Cloud, and Baidu AI Cloud, nearly every major domestic computing vendor placed their SuperPoD systems at the most prominent positions on their booths. This aligns with signals sent out by WAIC: the global focus of AI competition is shifting toward infrastructure. As a critical component of compute infrastructure, SuperPoDs are now stepping into the spotlight.

While goals remain aligned, technical approaches vary significantly.

Huawei follows an integrated path. The Ascend 950 SuperPoD (Atlas 950 SuperPoD), first publicly displayed this year, consists of 1,024 computing cards, features 256TB unified memory, and achieves NPU round-trip latency as low as 3 microseconds. Through unified memory addressing, these 1,024 cards can collaborate like a single complete computer.

IT Times reporters observed on-site that the entire system occupies nearly an entire exhibition wall, appearing from afar like a black "compute wall." Yet 1,024 cards are not the end. According to staff, the Ascend 950 SuperPoD can scale up to support interconnection of 8,192 chips—and potentially expand beyond 500,000-card clusters in the future.

In contrast to Huawei’s unified ecosystem, ZTE has chosen a more open route. Its OEX architecture supports heterogeneous hardware including CPUs, GPUs, switch chips, and NICs. By collaborating with domestic chip firms such as Biren, Muxi, Sichuan, and Tianshu Zhixin, ZTE aims to build an open, indigenous SuperPoD foundation, enabling users to freely select chip combinations based on specific business scenarios, thereby minimizing total cost of ownership (TCO).

Biren has focused its breakthrough on interconnectivity. Leveraging its proprietary BLink 2.0 interconnect protocol, 1,024 GPUs can share a single memory space, forming a logically unified "super GPU" capable of large-scale model training and inference. Biren also introduced the novel "NPO optical interconnect, distributed decoupled architecture" concept, aiming to overcome the bandwidth, latency, and distance limitations inherent in traditional copper-based interconnects.

Meanwhile, as the AI industry shifts from training to inference, TPUs are emerging as another viable option in the SuperPoD competition.

As China’s leading TPU company, Zhonghao Xinying unveiled its next-generation "Xuyu" AI chip. With mixed-precision floating-point compute reaching 896 TFLOPS and 8-bit inference capability of 1,792 TOPS, the "Xuyu" chip reduces single-chip power consumption by approximately 50% compared to similarly rated products.

Thanks to its native TPU architecture optimized for AI computation, a single SuperPoD can support up to 2,048 chips directly connected, enabling training of trillion-parameter large models, multi-agent collaboration, and massive inference tasks.

Yang Gongyifan, founder of Zhonghao Xinying, told IT Times that GPUs, originally designed for graphics rendering, inherently lack advantages in chip interconnectivity due to their underlying architecture. In contrast, TPUs were built from the ground up around large model training and massive parallel neural network computation—making them naturally suited for building SuperPoDs and easier to scale into ten-thousand-card-level systems.

Beyond chip vendors, cloud computing providers also view SuperPoDs as a cornerstone of AI infrastructure. Alibaba Cloud exhibited a compute system combining Zhenwu M890 chips with Panjue AL128 SuperPoDs. The Zhenwu M890 uses Pingtouge’s self-developed parallel computing architecture, featuring 144GB high-bandwidth VRAM and inter-chip connectivity bandwidth of up to 800 GB/s—capable of simultaneously meeting demands for large model training, inference, and intelligent agent applications.

Baidu showcased its Tianchi Compute Matrix based on Kunlunxin P800, supporting 256-card SuperPoDs and scalable to tens of thousands of cards. It is compatible with mainstream models including Wenxin, DeepSeek, Zhipu, and MiniMax.

Despite the diversity of approaches, the signal from this year’s WAIC is clear: the focal point of China’s domestic compute competition is shifting from individual chips to entire computing systems.

Model Evolution: The Catalyst for SuperPoDs

Why have nearly all companies turned to SuperPoDs this year? The answer lies not in the exhibition hall—but in the models themselves.

"SuperPoD isn't a new concept; it's the inevitable outcome of large model evolution," said Ding Yunfan, Vice President of AI Framework and Chief Architect of AI Software at Biren Technology, in interviews with IT Times and other media outlets.

As global large models accelerate iteration every three months, the competitive logic for domestic compute is undergoing transformation. Limited by process technology, current domestic GPUs still trail international leaders by 3 to 5 years in single-chip performance. Achieving leapfrog advancement via individual chips in the short term is unrealistic.

At the same time, the arrival of the Agentic AI era has triggered three distinct changes in large models—each intensifying demand for SuperPoDs.

The first change is the rise of MoE (Mixture of Experts) architectures, amplified by the explosion of Agent technologies. Previously, large models functioned as monolithic entities, invoking all parameters during each inference. Now, more models adopt MoE architecture, dynamically calling upon different "expert" networks based on task requirements. While computation becomes more efficient, data exchange between GPUs surges dramatically. "Expert parallelism demands extremely high interconnect bandwidth—if GPU communication can’t keep pace, even the strongest chips can’t deliver peak performance," Ding noted.

The second change is the rapid increase in model parameter counts. Where tera-parameter models were once considered large, today trillions of parameters have become the new benchmark. Kimi K3, released on July 16, boasts a staggering 2.8 trillion parameters—the largest open-source model globally. Industry experts predict that within a few years, models with five trillion parameters will emerge, further elevating demand for single-cluster compute capacity.

The third change is the dramatic expansion of context length. New applications like code agents and research agents continuously emerge, causing the number of tokens processed per task to multiply exponentially. The accumulated volume of input data and generated code significantly increases memory and compute demands—by an order of magnitude compared to past standards.

On one hand, there’s a hard ceiling on improving single-chip compute performance; on the other, expectations for model capabilities continue rising. Thus, "SuperPoDs have become a necessity," Ding concluded.

Optical Interconnects: Mainstream by 2028?

Yet when the metric for compute shifts from peak performance of individual chips to the effective compute capacity a full system can mobilize, the real challenge lies hidden within the racks.

After 1,024 GPUs form a SuperPoD, the true bottleneck determining compute ceiling is interconnect bandwidth, network architecture, software scheduling, and system-level coordination. In short, whether a batch of chips can be assembled into a highly efficient, cohesive system matters more than how fast each chip performs individually.

This also implies that system integration complexity rises exponentially—especially when GPU counts jump from hundreds to thousands, or even tens of thousands, where communication becomes the primary obstacle.

For decades, GPUs have relied on copper cables to transmit electrical signals. But with the advent of 800G and 1.6T high-speed interconnects, electrical signal transmission distances are shrinking and power consumption keeps climbing—pushing copper interconnects toward physical limits. "Copper cables can no longer meet future SuperPoD demands," a technician present remarked.

The solution lies in replacing electricity with light. Currently, four major optical interconnect technologies dominate: traditional pluggable (FRO), linear direct-drive (LPO), near-package optics (NPO), and co-packaged optics (CPO).

Ding stated that industry discussions have shifted away from mature FRO and LPO technologies toward the future-oriented NPO and CPO. "Especially NPO, which has become the core focus of cross-industry collaborative R&D."

Compared to traditional pluggable optical modules, NPO places the optical engine near the GPU or switch chip, drastically reducing electrical signal transmission distance. It eliminates high-power DSP (digital signal processor) chips, achieving better balance among bandwidth, latency, power, and cost. Additionally, it extends transmission distance to hundreds of meters—ideal for future large-scale SuperPoDs.

According to TrendForce, the CPO/NPO market is projected to grow from around $100 million in 2025 to over $39 billion by 2030—a five-year growth of nearly 400 times. Giants like Alibaba and Tencent have already designated NPO as their primary deployment axis in the near-to-mid term.

Thus, at this year’s WAIC, journalists clearly noticed that both optical module vendors, switch manufacturers, and other supply chain players began showcasing NPO-related products or explicitly outlining corresponding technical roadmaps. Although many products remain in R&D stages, the entire industry has entered a phase of coordinated advancement.

Ding believes that from a technological standpoint, China already possesses foundational capabilities to develop NPO-related products—with no insurmountable technical barriers. What’s needed now is R&D cycles and engineering validation. He anticipates that relevant products will begin rolling out within the next one to two years and enter real-world validation phases.

However, CPO remains underdeveloped domestically.

First, CPO requires integrating the optical engine directly into the compute chip package—demanding higher standards in chip design, advanced packaging, and manufacturing processes. Overall, the technical difficulty far exceeds that of NPO. China still lags behind global leaders in certain advanced process nodes.

Second, industrial division of labor differs. If, like NVIDIA, a company integrates compute chips and optical interconnects into a single chip, the value previously captured by optical module vendors gets absorbed by chipmakers—triggering a fundamental redistribution of industry profits.

"China is better suited for a collaborative ecosystem approach," Ding suggests. Under the NPO architecture, GPU vendors, switch makers, optical module suppliers, and others can leverage their respective strengths, find their positioning within the supply chain, and jointly capture the benefits of industrial growth. Such an ecosystem is healthier and more conducive to sustainable development of China’s domestic AI compute industry.

The industry remains in the stage of technical R&D and prototype validation. Biren plans to launch its NPO-based SuperPoD product next year and gradually transition into actual production environments. As the supply chain matures, NPO optical interconnects are expected to become the dominant solution for AI SuperPoDs by around 2028.

Scale: China Is Moving Faster

If communication and optical interconnects constitute the "inner workings" of SuperPoDs, then the factor truly determining how far they can go is another frequently mentioned term: engineeringization.

At this year’s WAIC, whether discussing intelligent agent factories, large model providers, or AI4S scientific intelligence platforms, the biggest challenge repeatedly cited was system engineering—something nearly impossible to avoid.

Yang Gongyifan offered an example: When vast numbers of chips form a unified cluster serving multiple clients simultaneously, reducing data exchange overhead in distributed computing becomes a core challenge for SuperPoDs. Meanwhile, issues like data isolation and privacy protection in multi-tenant environments, thermal management challenges posed by ten-thousand-card clusters, and software capabilities in distributed scheduling, cluster operations, and fault self-healing must all be addressed concurrently.

"SuperPoD competition is essentially an industrial chain battle," Yang said. A SuperPoD’s capability depends not just on chip performance but on system-level factors like network interconnectivity, cooling, software scheduling, and overall supply chain coordination. Packaging, switches, optical modules, liquid cooling, servers, scheduling software—these once-dispersed technologies are now tightly integrated due to the SuperPoD paradigm.

Interestingly, from Ding’s perspective, China may even be advancing faster than overseas counterparts in scaling SuperPoDs. Precisely because of the gap in single-card performance, domestic industries are more driven to solve problems through system-level innovation—not isolated breakthroughs, but systemic leaps.

This is also why Yang firmly chose the TPU route: As a specialized architecture, TPUs require far fewer customized operators than general-purpose GPUs, giving domestic vendors opportunities to rapidly catch up in specific domains and achieve "overtaking on a different track."

After four days of exhibitions, these black "compute walls" remained in many visitors’ phone albums. Perhaps, years from now, these photos will mark a precious beginning in China’s AI history.

Images / IT Times

This article comes from WeChat Official Account “IT Times” (ID: vittimes), author: Jia Tianrong

Source: IT Times